The present invention relates generally to the data processing field, and more particularly, relates to a method and apparatus for mapping multiple address spaces into a single bus, such as a peripheral component interconnect (PCI) bus.
Servers and other computer systems are becoming increasingly complex. One proposed server design contains two complete but separate processor architectures. For example, a first complex is a Pentium complex and the second complex is an IBM Power PC based processor used to provide an interface for storage media, local area network (LAN) adapters and an internal communication path of the first complex. The Power PC based I/O processor architecture is physically limited to a defined number of bits, such as 32 bits on both the peripheral component interconnect (PCI) bus and the internal processor buses. It is required that the Pentium memory be completely addressable from the PCI bus. In known designs, the amount of Pentium memory is limited such that both the I/O processor PCI bus address needs and the amount of Pentium memory both fit within a single 32 bit PCI bus address space.
It is desirable to allow an increased amount of Pentium memory, for example, in excess of 4 gigabytes (GB). A need exists for a way to access data on the PCI buses that accommodate both the I/O processor complex needs and the Pentium complex.
A principal object of the present invention is to provide a method and apparatus for mapping multiple address spaces into a single bus, such as a single peripheral component interconnect (PCI) bus. Other important objects of the present invention are to provide such method and apparatus for mapping multiple address spaces into a single peripheral component interconnect (PCI) bus substantially without negative effect; and that overcome many of the disadvantages of prior art arrangements.
In brief, a method and apparatus are provided for mapping multiple address spaces into a single bus, such as a single peripheral component interconnect (PCI) bus. The single bus, such as a single peripheral component interconnect (PCI) bus is coupled to a first processor complex and a second processor complex. An original address of a memory access is shifted to a unique address space for each originator/target of an operation. The shifted address is used on the single bus. Then the shifted address is shifted back to the original address for completing the operation on a destination bus.
In accordance with features of the invention, the original address of a memory access is shifted to a unique address space for each originator/target of an operation using a respective predefined value (+X1, +X2, or +X3) for shifting the original address above a predefined boundary for each originator/target of the operation. Shifting back the shifted address to the original address for completing the operation on the destination PCI bus uses a respective predefined value (xe2x88x92X1, xe2x88x92X2, or xe2x88x92X3) for the shifted back address to the original address for completing the operation on the destination PCI bus. Using the shifted address on the single PCI bus utilizes a dual address cycle (DAC) of the single PCI bus for the shifted address. Completing the operation on a destination PCI bus utilizes a single address cycle (SAC) of the destination PCI bus for the shifted back address to the original address.